1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device having substantially the same size as a semiconductor element or chip itself, hereinafter referred to as "chip-sized semiconductor device or package" and a process for making the same.
2. Description of the Related Art
A chip-sized package is a semiconductor device which has a substantially the same size as a semiconductor chip itself, in which a mounting substrate has a substantially the same size as a semiconductor chip and has external connecting terminals, such as solder balls, on a mounting surface thereof so that a semiconductor chip can be mounted on the mounting substrate by means of the external connecting terminals. Usually, the chip-sized package is a multi-pin type in which the external connecting terminals are arranged in a array on the mounting surface thereof.
FIG. 5 shows an example in which the lands 14 for connecting the external connecting terminals are arranged on the mounting surface of the semiconductor element 10. The semiconductor element 10 has electrodes 12 on the surface thereof. Wiring patterns 16 connect the electrodes 12 to the lands 14, respectively.
One example of methods for arranging the lands 14 on an electrode forming surface of the semiconductor element 10 is that, wiring patterns 16 are first formed on a passivation film of a semiconductor element 10 and then lands 14 are formed at the tip ends of the wiring patterns 16. Another example is that a wiring pattern film, used as an interposer, is first arranged on the electrode forming surface of the semiconductor element 10 and wiring patterns are then formed on the film to connect the lands 14 to the lands 14 and to the electrodes 12, so that the electrodes 12 are electrically connected to the lands 14, respectively.
In any case, it is necessary that the land, which is connected to the external connecting terminal, has a diameter of about 300 .mu.m. Therefore, if the lands 14 are arranged by themselves on the electrode forming surface of the semiconductor element 10, the spaces between the adjacent lands 14 will be very narrow and therefore the space for arranging the wiring patterns 16 are restricted. If the electrodes 12 are densely arranged and the number of pins is increased, the number of wiring patterns for connecting mutually between the electrodes and the lands will be increased and it will become difficult to preserve the enough spaces for arranging the wiring patterns 16.
If the wiring patterns 16 cannot be arranged on the electrode forming surface of the semiconductor element 10, a multi-layer structure of wiring patterns 16 must be used. However, such a multi-layer structure will make it difficult and complicated to produce the semiconductor devices, thereby reducing the reliability thereof.
Even if a wiring pattern film is arranged, as an interposer, to electrically connect the lands 14 to the electrodes 12 of the semiconductor element 10, forming such a wiring pattern film is complicated and also a connecting operation between the lands 14 and the electrodes 12 will be complicated and troublesome.